There is an increasing market demand for smaller, lighter, more powerful electronic devices and electronic devices with higher power densities, especially for use in electrical converter devices for maximizing energy conversion efficiencies in, for example, solar or wind power stations. It has become increasingly important to minimize energy losses as caused by, for example, electrical resistances in these devices. The development of more compact semiconductor devices and those with increased functionality has led to thinner semiconductor chips and packaging technologies, such as wafer level packaging (WLP). The development of more compact semiconductor devices has in particular led to thinner electronic devices, in particular to thinner vertical power transistors. Typically, vertical power transistors have two contacts on one face and one contact on an opposing face and in the on stage, current flows from a source contact on one face to a drain contact on the other face. Therefore, the vertical power transistor exhibits an on resistance between the drain and source terminals so that manufacturing a thinner vertical power transistor is a possible way of decreasing the on resistance of the transistor.